1. Field of the Invention
The present invention relates to semiconductor integrated circuits, in particular, it relates to semiconductor integrated circuits that have data input is from an external ROM, data transfer systems utilizing the semiconductor integrated circuits, and a method for data transfer for the semiconductor integrated circuit.
2. Description of the Related Art
There are semiconductor integrated circuits that have been developed with an embedded field programmable gate array (FPGA). An FPGA is a programmable logic device that allows user-design and operation. Lately, increases in integration, and as a result, increased appeal, have led to widespread usage of RAM FPGA circuits. RAM FPGA circuits allow reset of the circuit configuration each time the user turns on the power, as well as dynamic changes in the circuit configuration. Nevertheless, static random access memory (SRAM) is normally used with the RAM FPGA circuit, and because of the characteristics of volatile memory, the circuit data is erased each time the power supply is turned off As a result, configuration, which is an operation that promptly writes circuit data from an external read only memory (ROM), must be performed each time the power supply is switched on. In this case, configuration is an operation that includes inputting circuit-specific programming data into one or a plurality of FPGA, and connecting logic modules to surrounding internal connection path transistors to regulate functions. Immediately following configuration, the semiconductor integrated circuit is initialized, and then normal operation of the semiconductor integrated circuit begins.
With the conventional semiconductor integrated circuits and the data transfer systems such as those described above, the following problems occur: In an FPGA circuit where non-volatile memory (ROM) is used instead of RAM, design data written in the non-volatile memory can be easily read out externally. Accordingly, in the case of a ROM FPGA circuit, design data can be read out and parsed. Recent technology for FPGA circuits using ROM type non-volatile memory includes a technique where output buffer characteristics at the design data read-out terminal are changed after design data has been written to prevent the content of the internal non-volatile memory (ROM) from being externally read out. While this design data read out prevention using non-volatile memory (ROM) which can be used for IC products embedded with a non-volatile memory (ROM) FPGA circuit, it cannot be used for semiconductor integrated circuit products embedded with a RAM FPGA circuit. This is because circuit data must be input from the external ROM when the power supply is switched on, since the circuit data stored in the volatile memory (RAM) disappears when the power supply is cut off.
However, therein lies a problem where, since the FPGA circuit is all-purpose, analysis of the data stored in the external ROM allows for easy reading as to what kind of circuit should be formed and how the FPGA circuit should function. Thus, if a RAM FPGA circuit is used, since design data is stored on an external ROM and both the FPGA circuit and the external ROM are mounted on the same board, the confidential information contained in the design data can be easily revealed through analysis of the external ROM data. Among other things, this situation makes so-called “dead” copies possible. Accordingly, a semiconductor integrated circuit embedded with an FPGA circuit capable of protecting the secrecy of design data is also desired for a semiconductor integrated circuit embedded with a RAM FPGA circuit.
Similarly, in a semiconductor integrated circuit or system which has an internal CPU and operates by reading software in or from an external ROM, confidential software design data can be easily revealed through analysis of external ROM data. Since CPU instructions are generally published, the software program codes can easily be interpreted by analyzing ROM data. Accordingly, a high-security semiconductor integrated circuit that does not permit either design data or software read out is desired.